Recently, a semiconductor memory device has been developed to a high-speed and high-integrated memory with the technical improvement and is used for various products from large size home appliances to small size mobile products.
Such a semiconductor memory device is comprised of a plurality of memory cells on which data signals are recorded, and a data signal is read as ‘1’ or ‘0’ according to the amount of electric charge accumulated in the memory cell. However, since the electric charge accumulated in the memory cell is discharged with the lapse of time, it becomes difficult to determine a data signal as ‘1’ or ‘0’. For this reason, an auto refresh operation is performed to amplify and record again a data signal recorded in the memory cell at a predetermined time interval.
An auto refresh operation is classified into an All Bank Refresh for refreshing all banks of a chip and a Per Bank Refresh for performing refreshing per bank. Typically, a refresh signal generating circuit is provided in a semiconductor memory device to generate a refresh signal to trigger auto refresh operations.
FIG. 1 is a diagram illustrating a conventional refresh signal generating circuit.
As shown in FIG. 1, the conventional refresh signal generating circuit comprises a clock enable signal buffer 1, a clock buffer 2, a command address buffer 3, a chip select signal buffer 4 and a command decoder 5.
The operation of the refresh signal generating circuit of FIG. 1 is as follows.
First, the clock enable signal buffer 1 generates first and second buffer enable signals BEN and BENB in response to an external clock enable signal CKE.
The clock buffer 2 receives external clocks CLK and CLKB and generates a first internal clock ICLK_CAB and a second internal clock ICLKP4 in response to the second buffer enable signal BENB.
The command address buffer 3 receives external command address signals CA<0:3> and a reference voltage VREF and generates an internal command address signals ICA<0:3> in response to the first internal clock ICLK_CAB from the clock buffer 2. Here, the command address buffer 3 is enabled in response to the first buffer enable signal BEN from the clock enable signal buffer 1. The chip select signal buffer 4 receives an external chip select signal CS and a reference voltage VREF and generates an internal chip select signal ICSB in response to the first internal clock ICLK_CAB. Here, the chip select signal buffer 4 is enabled in response to the first buffer enable signal BEN.
The command decoder 5 receives the internal command address signals ICA<0:3> generated in the command address buffer 3 and the internal chip select signal ICSB generated in the chip select signal buffer 4 and decodes them, to generate an all bank refresh signal AREFP in response to the second internal clock ICLKP4. The all bank refresh operation is performed in all banks of a chip in response to the all bank refresh signal AREFP. In this case, an access for general reading or writing operation is limited in all banks of a chip.
However, the conventional clock buffer 2 and command address buffer 3 maintain an enable state even in an all bank refresh operation, and continues an internal operation in response to toggling external clocks CLK and CLKB and the command address signals CA<0:3>, causing unnecessary current consumption.